Monolithic integrated structure including fabrication and packaging therefor

ABSTRACT

A method of making a monolithic integrated semiconductor structure that has a plurality of functionally isolated individual cells that are electrically interconnected. Each of the cells is an object of mirror image cell that is vertically, horizontally and diagonally displaced from the object cell. The plurality of cells provide a memory array with electrical components of each memory cell composed of active and passive semiconductor devices. Other importance aspects of the structure include underpass connections and active devices in a common portion of the structure which are electrically interconnected at the same node potential by means of a highly doped buried region within the common portion of the structure.

MONOLTTHIC INTEGRATED STRUCTURE INCLUDING FABRICATION AND PACKAGING THEREFOR Inventors: Benjamin Agusta; Paul H. Bardell;

Paul P. Castrucci, all of Poughkeepsie; Robert A. Henle, Hyde Park; Raymond P. Pecorato, Poughkeepsie, all of N.Y.

Assignee: International Business Machines Corporation, Armonk, NY.

Filed: Apr. 16, 1970 Appl. No.: 33,127

Related U.S. Application Data Division of Ser. No. 539,210, March 31, 1966, Pat. No. 3,508,209.

1 51 May 8, 1973 [56] References Cited UNITED STATES PATENTS 3,295,031 12/1966 Schmitz ..3l7/235 3,333,326 8/1967 Thomas et al. ....29/577 UX 3,392,442 7/1968 Napier et a1. ..29/589 X Primary Examiner-John F. Campbell Assistant Examiner-W. Tupman Attorney-Hanifin and Jancin and George 0. Saile [57] ABSTRACT A method of making a monolithic integrated semiconductor structure that has a plurality of functionally isolated individual cells that are electrically interconnected. Each of the cells is an object of mirror image cell that is vertically, horizontally and diagonally displaced from the object cell. The plurality of cells provide a memory array with electrical components of each memory cell composed of active and passive semiconductor devices. Other importance aspects of U.S. Cl. ..29/577, 29/578, 29/589 1m.c1. ..B0lj 17/00, H011 1/16 the Structure include underpass connections and Field of Search ..29/5s9,577,5771c, devices in a common Portion of the Structure 29578 which are electrically interconnected at the same node potential by means of a highly doped buried region within the common portion of the structure.

1 Claim, 40 Drawing Figures FORN SENICONDUOTOR WAFER REOXIDIZE WAFER TURN RETAI- IIIIEROOIIIIEC' OF P- TYPE CONDUCTIVITY sumct nous AND OIINIC cmmcrs OXIDIZE WAFER SURFACE I NASA AND ETCN HOLES IN OXIDE LAYER ABOVE EPITAXIALLY GROWN REGIONS APPLY SPUTTERED OXIDE OVERCOAT NASII AND ETCH HOLES IN OXIDE LAYER I FORN N REGIONS IN THE WAFER SURFACE BY DIFFUSION OXIOIZE WAFER SURFACE T0 OIFFUSE P TYPE BASE DIODE,ANO RESISTOR REGIONS INTO ISOLATED EPITAXIALLY GROWN REGIONS I OXIDIZE SURFACE 1110 nmve m IIIPURITIES FORIIIIIG THE I aasemoomuo RESISTOR nee IIASK AND ETGH TERMINAL HOLES IN SPUTTERED OXIDE OVERCOAT LAYER EVAPORATE CR, CU, AND AU INTO TERIIINAL ROLES IONS EVAPORATE OVERSIZE PB-SN e?TUIIILL YTIIOR 1 LAYER or M 1m mam/11 RITIES T0 ronu ENITTER I REGIONS 111mm TIIE 11s:

REGIONS DICE WAFER INTO ON THE WAFER SURFACE AND CHIPS OXI DIZE SURFACE OF I OXIOIZE SURFACE AND DRIVE IN INPURITIES FORNIIIG THE ENITTER REGIONS APPLY NONOLITIIIO INTEGRATED CHIPS ON PRIN- I TED LAND PATTERNS ON EPITAXIALLY GROWN LAYER EVAPORATE GOLD ONTO EX- CERAIIIO SUBSTRATE TION REGIONS AND CON- t POSEDSEIIICORDUCTOII RISK AND EIIHIIIEIIIORI SURFACE AND OIFFUSE c010 INTERCONNECT IIONOLITIIIC OFCHANNELS 11 THE 0110: 1110 men INNONOXIDIZIIIC IIITECRATEDCIIIPS to 11m EXPOSIIIG THE SENI- 111105111515 PRINTED LAND PATTERN conoucmn sumct L "mmeg 571 1111511 WAFER AND ntcoven OF TRANSISTOR DEVICES NECTOR REGIONS INTO THE EXPOSED SENICONDUCTOR SURFACE CONTACTS CONDUCTOR REGIONS TO DESIRED SENI- PATENTE-DIIIY 81915 SHEET 01 OF 23 FIG. I

7 I FORM SEMICONDUCTOR WAFER REOXIDIZE WAFER FORM METAL INTERCONNEC- OF P TYPE CONDUCTIVITY SURFACE TIONS AND OHMIC CONTACTS OXIDIZE WAFER SURFACE MASK AND ETCH HOLES IN OXIDE LAYER ABOVE EPITAXIALLY GROWN REGIONS APPLY SPUTTERED OXIDE OVERCOAT MASK AND ETCH HOLES IN OXIDE LAYER I FORM N REGIONS IN THE WAFER SURFACE BY DIFFUSION OXIDIZE WAFER SURFACE TO CREATE DEPRESSION ABOVE N+ REGIONS REMOVE OXIDE LAYER OXIDIZE SURFACE OF EPITAXIALLY GROWN LAYER MASK AND ETCH A NETWORK OF CHANNELS IN THE OXIDE LAYER EXPOSING THE SEMI- CONDUCTOR SURFACE DIFFUSE P TYPE ISOLA- TION REGIONS AND CON- NECTOR REGIONS INTO THE EXPOSED SEMICONDUCTOR SURFACE MASK AND ETCH HOLES IN OXIDE LAYER FOR FORMING I CONTACTS TO DESIRED SEMI- OIFFUSE P TYPE BASE,

DIOOE,AND RESISTOR REGIONS INTO ISOLATED EPITAXIALLY GROWN REGIONS I OXIDIZE SURFACE AND DRIVE IN IMPURITIES FORMING THE BASE,DIODE,AND RESISTOR REGIONS I MASK AND ETCH HOLES IN OXIDE LAYER ABOVE BASE REGIONS I OIFFUSE IN N TYPE IMPU- RITIES TO FORM EMITTER REGIONS WITHIN THE BASE REGIONS OXIDIZE SURFACE AND DRIVE IN IMPURITIES FORMING THE EMITTER REGIONS EVAPORATE GOLD ONTO EX- POSED SEMICONDUCTOR SURFACE AND DIFFUSE GOLD INTO WAFER IN NONOXIDIZINC ATMOSPHERE ANNEAL WAFER AND RECOVER OF TRANSISTOR DEVICES CONDUCTOR REGIONS MASK AND ETCH TERMINAL HOLES m SPUTTEREO oxms OVERCOAT LAYER EVAPORATE CR, CU, AND AU INTO TERMINAL HOLES EVAPORATE OVERSIZE PB-SN PADS ONTO CR,CU,AU LAND PORTIONS u E LT PADS TO REFLOW am T0 LANDS DICE WAFER INTO CHIPS INTERCONNECT MONOLITIIIC INTEGRATED CHIPS TO PRINTED LAND PATTERN INVENTORS BENJAMIN AGUSTA PAUL H. BARDELL PAUL P. CASTRUCCI ROBERT A. HENLE RAYMOND P. PECORARO ATTORNEY PVENIEUVY 3,731,375

SHEET OH OF 23 FIG. IG FIG. 36

vFORM ACTIVE AND/ OR PASSIVE COIPLETE .m o

simcomcw" DEVICES oxmmon OPERATIONS EXCEPT A MONOLITHICSEIIICONDUCTOR snwcruns FOR Hm WW5, TO FORM ACTIVE AND/OR PASSIVE DEVICES IN A MONOLITHIC SEMICONDUCTOR STRUCTURE FORM THE FINAL OXIDE LAYER ON THE SURFACE OF THE MONOLITHIC SEMICONDUCTOR STRUCTURE REMOVE A SELECTED PORTION OF THE FINAL OXIDE LAYER TO EXPOSE SEMICONDUCTOR SURFACE REMOVE A SELECTED PORTION OF THE FINAL OXIDE LAYER TO EXPOSE A SURFACE PORTION OF THE SEMICONDUCTOR STRUCTURE OIFFUSE CARRIER LIFETIME KILLERS INTO SEMICONDUCTOR STRUCTURE THROUGH THE EXPOSED SURFACE IN A NON-OXIDIZINC OIFFUSE CARRIER I ATMOSPHERE LIFETIME KILLERS INTO THE EXPOSED SEMICONDUCTOR SURFACE IN A NON-OXIDIZINC ATMOSPHERE l PERFORM FINAL DIFFUSION r- "1 OPERATION TO FORM DESIRED I PERM" A NOII'OXID'ZING NEIL I SEMICONDUCTOR DEVICES mmour A OPERATION TO INCREASE THE I FINAL mm" STEP CURRENT CAIN or THE ACTIVE DEVICES TOTAL CARRIER LIFETIME KILLER DIFFUSION TIME (INCLUDING FURNACE RECOVERY TIME) TIME A Tm 50mm mm) mm) mm 970,0 503 40-50;; IS-I'IB IB-ITT IO-Ilr -91 IOOO'C we? FIG. 26

PATENTEUHAY ems 3,731,375

saw 05 0F 23 P- -10T P m STEP 1 N m- J J m 1 N+ I P l 161 STEP 5 STEP 2 54] 52T 36T 301 18T 321m) 1'\ 4N 20T-1 lfifl LL A-24I P m N P+ N P+ 241 m 1eT-} L L 1 1 16T STEPS STEP 4 FIG.6A

WORD LINE PATENTEDMAY 3' 3,731,375

SHEET user 23 FIG.2

PATENTED W 31973 SHEET U'IUF 23 PMENTED MAY 8 5 SHEET UBOF 23 FIG.2L

PATENTEUHAY ems 3,731,375

SHEET USUF 23 PATENTED 81973 3,731,375

' SHEET lUUF 23 PATENTED HAY 81975 SHEET MW 23 T ||c.l wwu l N n w 4 a m w V d T if l i| L u u u u u 4 /mvm R; e m |ir|i| iililn F w 2 n 6 w M R T vll T L u u C C A A m FIIMRIiIRII LiiU Y Y 5 GND FIG.5

VERTICAL PLANE HORIZONTAL PL OBJECT (WORD) mRRoR IMAGE (WORD) MIRROR IMAGE (w DIAGONAL IMAGE (WORD) SHEET 170F 23 PATENTED MAY 81973 1w; 2:: 25 3 3 10 2: OE zw mm PATENTED MAY 8 I975 SHEET 180F213 FUGJBA PATENTED MAY 8 75 SHEET 19 HF 23 FIG. 19 

